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[Other resource] !061210[1].pdf

Description: 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片
Platform: | Size: 242001 | Author: youren | Hits:

[Other resource] FIFO_BEFORE

Description: 是基于fpga的FIFO乒乓操作，后面是与SDRAM接口的，这样主要方便sdram的刷新-fpga is based on the FIFO Table Tennis operation, and is behind SDRAM interface, This major update to the convenience sdram
Platform: | Size: 212389 | Author: eva | Hits:

[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[Other resource] fifo_generator_ug175

Description: 该文档是有关利用XINLIX的FPGA如何实现FIFO的生成及如何应用的文章。
Platform: | Size: 715334 | Author: cobain | Hits:

[Other resource] vr_fifo

Description: 可预取的fifo 的fpga 设计代码，满足异步时钟的操作
Platform: | Size: 573512 | Author: yy | Hits:

[Other resource] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。
Platform: | Size: 10619 | Author: David.Mr.Liu | Hits:

[Other resource] sram

Description: FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等
Platform: | Size: 270755 | Author: 王刚 | Hits:

[Other resource] asyn_FIFOandFPGAdesign

Description: 一篇关于FIFO设计以及FPGA设计的文章
Platform: | Size: 453446 | Author: Roger | Hits:

[Windows Develop] USB-slavefifo

Description: 本组程序包括FPGA程序，固件程序和上位机程序，实现USB的数据传输功能，采用Slave Fifo模式，上位机程序利用Cypress公司提供的库函数进行开发
Platform: | Size: 383419 | Author: 林颖 | Hits:

[VHDL-FPGA-Verilog] uart from opencores

Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted.
Platform: | Size: 9216 | Author: 熊明 | Hits:

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

Description: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Platform: | Size: 43008 | Author: 立立 | Hits:

[VHDL-FPGA-Verilog] AD0809

Description:
Platform: | Size: 4339712 | Author: 侯训平 | Hits:

[VHDL-FPGA-Verilog] a1

Description: 基于FPGA的B超数据采集功能，根据输入图像的束同步与帧同步信号，采用中断控制进入FIFO的图像数据的读写操作！-FPGA-based B-data collection capabilities, according to the input image beam synchronization and frame synchronization signal used to control access to FIFO interrupt the operation of image data read and write!
Platform: | Size: 3072 | Author: 齐磊 | Hits:

[VHDL-FPGA-Verilog] fifo_FPGA

Description: 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
Platform: | Size: 887808 | Author: 郑韬 | Hits:

[VHDL-FPGA-Verilog] tx_rx_fifo

Description: 通过串口将接收到的数据存入fifo,fifo存满后使能串口发送功能，将接收到的数据发送出去(Use fifo to realize the receive and send function of the uart. The function is no problem.)
Platform: | Size: 3791872 | Author: Pgaf | Hits:

[USB develop] 13_usb_test

Description: READ 16BIT DATA FROM EP2 FIFO AND SEND TO EP6 FIFO
Platform: | Size: 1006592 | Author: ZHOUHAIJUN | Hits:

[VHDL-FPGA-Verilog] fifo_test

Description: fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
Platform: | Size: 1957888 | Author: dufanbao | Hits:

[Books] Clifford_E._Cummings经典论文合集

Description: FPGA中经典模块的实现相关介绍文档，经典(FPGA in the classic module of the implementation of the document, the great God of foreign papers)
Platform: | Size: 2029568 | Author: gxgone | Hits:

[Com Port] tx_interface_project

Description: 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
Platform: | Size: 850944 | Author: lionel_messi | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:
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